1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to a semiconductor memory device for outputting at a high speed a stored data signal at an externally designated interval. The present invention has a particular applicability to a video RAM and a field memory for image processing.
2. Description of the Background Art
With the recent development of image processing technology, the development of technology has been rapidly progressing for e.g. color display on cathode ray tube of personal computers, three dimensional display of CAD system, enlargement and reduction of images, multi-windowing of the screen, and enhancement of resolution. In addition, computer graphics for displaying the result of numerical calculation by super computers and the like have also been noted. Under such circumstances, various video memory devices have been developed for storing a digital image signal. A video RAM is known as a random access memory optimized for storing image data and is capable of performing random access and serial access.
FIG. 10A is a block diagram showing an overview of a video RAM. The video RAM 1' comprises a dynamic random access memory cell array 2 for storing image data, a data transfer bus 102 for transferring the data read from the memory cell array 2, and a serial register 4 for serial access. The memory cell array 2 is connected to a central processing unit (CPU) 201 through a random access port, and is random accessed by CPU 201. The serial register 4 for serial access serially outputs image data read through the data transfer bus 102 through a serial access port responsive to an externally provided serial clock signal SC. The outputted serial data is applied to a CRT controller 202. The CRT controller 202 includes a latch circuit 206 for latching the output serial data. The data latched to the latch circuit 206 is converted into an analog signal by a D/A converter 207. An RGB processor 208 responds to the converted analog signal and generates R, G and B signals for display on a CRT display 203 by image processing. The R, G and B signals are applied to the CRT display 203. The CRT controller 202 also includes synchronizing control circuit 209 for performing synchronizing control of the CRT display 203 in response to a synchronizing control signal generated from a circuit 209, and display an image according to the R, G and B signals. It is pointed out that in the above mentioned operation, the CPU 201 generates a various kinds of control signals for controlling the video RAM 100 and the CRT controller 202.
Also in the field of image technology, such as recent television and video tape recorder (VTR), there has been a greater demand for digital signal processing for image signal. More specifically, digital television, digital video tape recorder and the like are being developed. In these equipments, enhancement of image quality and multifunction of image are realized by digital processing of image signal. Under the circumstances, a field memory has already been developed which stores the image data to be displayed on the whole screen.
FIG. 10B is a schematic diagram showing an overview of a field memory. Referring to FIG. 10B, the field memory 300 comprises a serial input register 301 for receiving serial data, a field memory cell array 303 for storing the data to be displayed on the whole screen, a serial output register 305 for holding the output data, and data transfer buses 302 and 304. The serial input register 301 receives the data provided from an A/D converter 204 through a serial input port in response to a clock signal SC1. The serial output register 305 applies the data read from the memory cell array 303 to a D/A converter 205 through a serial output port in response to the clock signal SC2. As described above, a video RAM generally has two input/output portions, namely, a random access port and a serial access port, whereas a field memory generally has a serial input port and a serial output port. It is pointed out that these two memory devices have a common point in that they both serially output the data read from the memory cell array in response to an externally provided serial clock. Since serial outputting of the read data is performed in response to one serial clock signal, the data for displaying a picture or an image is obtained at a high speed. Although the invention is generally applicable to a video RAM and a field memory, for the purpose of simplification, only the application to a conventional video RAM will be described below.
FIG. 11A is a block diagram of a conventional video RAM. The video RAM is seen in U.S. Pat. No. 4,633,441. It is assumed that the video RAM 1' has memory cells MC arranged in 256 rows.times.256 columns. Referring to FIG. 11A, the video RAM 1' comprises a memory cell array 2, a row address buffer 11 and a column address buffer 12. A row decoder 13 is responsive to row address signals AX0 to AX7 for designating a word line WL, and a column decoder 14 is responsive to column address signals AY0 to AY7 for selecting a bit line pair. A sense amplifier 3 amplifies the data signal read from the designated memory cell. A serial register 4 holds the amplified data signal. A counter 7' generates internal address signals SY0 to SY7 for serial output based on start addresses SA0 to SA7 applied from the column address buffer 12. A serial decoder 6 is responsive to the generated internal address signal for designating stages of the serial register 4. A random access port is connected to a data bus line 15. More specifically, a parallel data input PDI and a parallel data output PD0 are connected to the data bus line 15, while serial access port, namely, a serial data input SDI and a serial data output SDO, is connected to a serial bus line 5.
A clock signal generating circuit 16' is connected to receive a row address strobe signal RAS, a column address strobe signal CAS, a serial clock signal SC and a data transfer signal DT. The clock signal generating circuit 16' generates the required control clock signal in response to the externally provided signals.
In operation, the memory cell designated by the address signals AX and AY is accessed through the random access port, namely, the parallel data input PDI and the parallel data output PDO. Meanwhile, serial data is inputted and outputted through the serial access port, namely, the serial data input SDI and the serial data output SDO in response to the internal address signal generated by the counter 7'. The serial register 4 includes 256 register devices. In serial output operation, the row decoder 13 selects one externally designated word line, and digital signals stored in memory cells connected to the word line are therefore amplified by the sense amplifier 3. The counter 7' responds to a serial clock signal SC generated from the clock signal generating circuit 16', and generates sequentially increasing internal address signals SY0.about.SY7. The serial decoder 6 responds to the internal address signals SY0.about.SY7, and selects register devices in the serial register sequentially so that the data signals held in the respective register devices are read out.
FIG. 11B is a block diagram of the counter 7' shown in FIG. 11A. Referring to FIG. 11B, the counter 7' includes 8 cascaded count units 700.about.707. Each of the counter units 700.about.707 is connected to receive a serial clock signal SC. The counter units 700.about.707 are initialized according to initiation addresses SA0.about.SA7 applied through the column address buffer 12, and then generates sequentially increasing internal address signals SY0.about.SY7, in response to the serial clock signal SC. The internal address signals SY0.about.SY7 are applied to the serial decoder 6.
FIGS. 12A and 12B are timing charts showing the serial input and the serial output of data. The serial access functionis realized in response to the externally provided serial clock signal SC. More specifically, in the case of serial data input, as shown in FIG. 12A, an internal address signal is counted up in response to the rise of a serial clock signal SC and the data signal SDI externally provided in response to the internal address signal is inputted to the video RAM. Similarly, in the case of serial output, as shown in FIG. 12B, an internal address signal is incremented in response to the rise of a serial clock signal SC. The data SDO designated by the internal address generated by the counter 7' is serially outputted.
Referring to the timing chart shown in FIG. 13, the serial output operation of the video RAM shown in FIG. 11A will be described in more detail. First, after a column address ADx is applied in response to the fall of the signal RAS, a column address ADy is applied in response to the fall of the signal CAS. The column address buffer 12 shown in FIG. 11 applies the column address ADy to the counter section 7' as start addresses (SA0 to SA7). The counter 7' starts counting from the applied start address ADy. Accordingly, the counter 7' generates an internal address signal starting from the start signal ADy in response to the clock signal SC. The serial decoder 6 sequentially designates the registers provided in the serial register 4 in response to the generated internal address signal.
Each register in the serial register 4 holds the data signal read by the sense amplifying 3 from the memory cell in the memory cell array 2. Since each register in the serial register 4 is sequentially designated by the serial decoder 6, serial data are outputted at a high speed. More specifically, as shown in FIG. 13, the data D0, D1, D2, . . . are outputted designated by the incrementing addresses ADY, AD (y+1), AD (y+2), . . . , being incremented from the applied start address ADy (where the address ADx is constant).
In the field of the conventional image processing, in order to carry out, for example, reduction of image and the mosaic forming of images, it is necessary to selectively sample the data at a predetermined address interval from a set of data (e.g. 1 frame of data) for configuring one image. More specifically, the reduced or mosaic formed picture is displayed on a screen based on the picture data selectively sampled. Conventionally, after all of one set of the data was read from the video RAM, the desired data was sampled from the read data by software processing.
FIG. 14 is a timing chart showing successive data being read from the video RAM shown in FIG. 11. More specifically, as shown in FIG. 14, first all one set of data for configuring one image is read irrespective of being used or not. Accordingly, although the data D0 to D9 are read successively in response to the serial clock SC, only the data D0, D4 and D8 are required among these data in order to configure the reduced image or picture for the mosaic formed image. That is, only the data D0, D4, and D8 are used, and other data are not used. The sampling of these data D0, D4 and D8 to be used is performed by software processing, for example, in the cathode ray tube controller 202 shown in FIG. 9.
Thus, since one set of data is all serially read from the video RAM 1' shown in FIG. 11 irrespective of necessity, it takes longer than required to read the data. For instance, in the example shown in FIG. 14, it takes 9 clock cycles to obtain the required 3 data, D0, D4, and D8, so that it requires the period T1.